1. Field of the Invention
The present invention relates in general to an ESD protection component. In particular, the present invention relates to an ESD protection component combining metal oxide semiconductor field effect transistor(MOS FET) with semiconductor controlled rectifier (SCR).
2. Description of the Related Art
As technology advances, ESD durability has become an increasing concern for integrated circuit (IC) manufacture. As semiconductors have advanced into deep submicron regimes, the resulting scaled-down semiconductors, shallower doping junction depths, thinner gate oxide layers, lightly-doped-drain structures (LDD), shallow trench isolation (STI) and salicide processes are less tolerant stress. Therefore, special ESD protection circuits must be deliberately designed around the I/O port of the IC to prevent damage from ESD stress.
Normal ESD protection circuits have a parasitic npn bipolar junction transistor (BJT) in the output stage NMOS FET to release ESD stress. The output stage NMOS FET is usually strong enough to withstand strong current.
Alternatively, SCR formed across the I/O pad and the power line is used as the ESD protection component. Less heat is generated from the SCR due to its low holding voltage. The SCR thus endures high ESD stress and is a good ESD protection component. In conventional technology, NMOS FET is used to decrease the trigger voltage of the SCR. FIG. 1a shows a conventional NMOS triggered low-voltage SCR (NTLSCR). FIG. 1b shows a cross-section of a line aa′ in FIG. 1a. The SCR is composed of a P+ doped region 64, an n-well 62, a p substrate 60 and an N+ doped region 66. Special attention is paid to the configuration of the NMOS FET and the SCR to obtain a smaller layout area with better ESD protection ability.
In U.S. Pat. No. 5,742,085, an NMOS FET is formed between two SCR. When the drain of the NMOS FET is broken down, both SCR are triggered simultaneously.